Optimizing Circuit Partitioning by Implementing Data Mining and Vhdl Tools Pertinent to Vlsi Design

The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to subdivide multi –million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clustering technique by applying two clustering algorithms K-Means and PAM(Partitioning around mediods). These two algorithms were tested on a BCD to Seven Segment Code Converter circuit consisting of eight nodes and also were tested on a circuit consisting of 15 nodes. The two algorithms were implemented on VHDL. The tested results show that PAM yield better subcircuits than K-Means.